In the normal course of designing integrated circuits, one solves the problem of signal propagation delay by attempting to minimize such delay. To this end, the manufacturers of integrated circuits have developed smaller, thinner, and more densely packed structures, thereby achieving speeds of operation that could scarcely have been dreamed of a decade ago. By keeping the delay through any given gate stage small enough, the overall response time of the circuit may be kept below the predetermined design level.
There are, however, certain applications where the "less-is-better" approach does not suffice. Rather, these applications require that gate delays be kept highly stable under a wide variety of conditions. An example is circuitry for deskewing electrical signals within automatic test equipment used for testing integrated circuits.
Typical automatic test equipment applies a plurality of input signals to selected pins of a device under test ("DUT") which in response produces a plurality of output signals at other selected pins. The test equipment senses the output signals and analyzes them for their compliance with quality control standards.
Under control of the test system computer and its programs, the test equipment can perform tests on a variety of integrated circuit devices. Because of the versatility of the test equipment, a particular input signal may be applied to a DUT pin over a number of different paths, and the output signals may follow a number of different paths from a DUT pin to the analysis circuitry. The resultant timing variations, commonly termed skew, must be corrected to assure the validity of the test being performed.
A typical automatic test system has in excess of 100 pins, each with associated receivers and drivers. Thus, it is required to adjustably correct hundreds of timing paths. There have been developed programmable delay lines, typically hybrid devices having a data input and a signal input and output. A binary code applied to the data input results in a corresponding propagation delay between the signal input and the signal output. Typical resolution requirements are illustrated by the Fairchild Series 20 Test System which specifies that any input timing edge can be placed anywhere from the beginning of a cycle up to 20 ns before the end of the following cycle, in increments of 156 ps.
As faster and faster test systems are designed, the resolution requirements become even more stringent. However attempts to provide programmable delay elements having a resolution at the level of 10 ps have been frustrated by apparently spurious timing fluctuations and signal distortions within the integrated circuit portion of the delay device.